Contact Information:

        College of Computer Science
        Inner Mongolia University                         Tel: ++86-471-4993510
        Huhhot, Inner Mongolia                            Fax: ++86-471-4992341
        010021                                                    Email: liqiang.he@gmail.com
        P.R. China

Working Experience:
        Inner Mongolia University, Huhhot, China, Lecturer, Feb. 2008 - Present
        University of Cyprus, Nicosia, Cyprus, Research Scientist, Oct. 2006 - Jan. 2008
        IRISA-INRIA, Rennes, France, Post-doc, Sep. 2005 - Sep. 2006
        Inner Mongolia University, Huhhot, China, Lecture, Jul. 1995 - Sep. 1999

Education:
        Ph.D, Jul. 2002 - Jul. 2005, Institute of Computing Technology, Chinese Academy of Sciences
        M. Eng, Sep. 1999 - Jul. 2002, Inner Mongolia University
        B. Sc., Sep. 1991 - Jul. 1995, Inner Mongolia University

Courses:

       Computer Architecture - Autumn Semester, 2010

        Operating System - Autumn Semester, 2010

        Computer English - Spring Semester, 2010

        Parallel Processing - Spring Semester, 2010

                For other courses in previous years, please see here.

Students:

       Yun Wei                (Ph.D student)       From Autumn 2009

        Sun Yan                (master student)     From Autumn 2008 
        Cao Hao                (master student)    From Autumn 2008
        Zhang Chaozhong   (master student, cosupervised with Associate Professor Xu Xiaodong)    From Autumn 2008
        Zhang Guangyong   (master student, cosupervised with Associate Professor Xu Xiaodong)    From Autumn 2008
        You Congwei         (master student)    From Autume 2008
        Wu Xiaohong         (master student)    From Autume 2008
        Zhang MingZhe       (master student)    From Autumn 2009
        Tong Xiaowu          (master student)    From Autumn 2009
        Peng Can                (master student)    From Autumn 2009
        Sun Yahong            (master student)    From Autumn 2009
        Lang Lingling          (master student)    From Autumn 2009
        Jiang Jingdong         (master student)    From Autumn 2009

Projects:

        1. Many-Core Simulation on GPU Platform  (Zhang Guangyong and Liqiang He)

        2. Thermal-Aware Floorplanning and Thread Mapping  (Cha Narisu and Liqiang He)

        3. Speedup Sequential Program Execution on Multi-Core Processor (Sun Yan and Liqiang He)

Publications:

Journal papers:

[1] L. He, Generation of test suite for float-point arithmetic based on IEEE754 standard, Computer Engineering, Vol:30, No.19, pp.38-41, ISSN:1000-3428. (Chi­nese Language)

[2] L. He and Z. Liu, An Instantaneous IPC Based Instruction Fetch Policy for SMT Processors, Chinese Journal of Computers in 2007. (Chi­nese Language)

[3] L. He and Z. Liu, An Effective Instruction Fetch Controlling Mechanism for SMT Processors, Chinese Journal of Computers, 2006, Vol.4 pp. 535-543.(Chi­nese Language)

[4] L. He and Z. Liu, A QoS Capable Fetch Policy for SMT Processors, Chinese Journal of Computer Research and Development, 2006, Vol.11, pp.1980-1984.(Chi­nese Language)

Internationalconference:

[1] L. He, and Z. Liu, An Effective Instruction Fetch Policy for Simulta­neous Multithreaded Processors, 7th International Conference on High Perfor­mance Computing and Grid in Asia Pacific Region, pp.162-168, July 20-22, 2004, Tokyo, IEEE Computer Society (ISTP index)

[2] L. He and Z. Liu, Improving Performance Through Combining Branch Classifier and Fetch Controller into SMT Processors, The 2004 International Conference on Parallel and Distributed Processing Techniques and Applications, pp.1561-1567, June 21-24, 2004, USA, CSREA Press

[3] L. He and Z. Liu, A New Value Based Branch Predictor for SMT Proces­sors, The IASTED International Conference on Parallel and Distributed Com­puting and Systems (PDCS 2004), pp.775-783, Nov. 9-12, 2004, USA, ACTA Press (nominated the best paper)

[4] L. He and Z. Liu, An Effective Simultaneous Multithreaded Processor Front-end, The IASTED International Conference on Advances in computer Science and Technology (ACST 2004), pp.228-233, Nov. 22-24, 2004, USA, ACTA Press

[5] L. He and Z. Liu, A QoS Capable Fetch Policy for SMT Processors, ICENCO 2004, Dec. 28-30, 2004, Egypt, Proceeding CDROM

[6] L. He and Z. Liu, Improving Accuracy of Perceptron Predictor Through Correlating Data Values in SMT Processors, IEEE International Symposium on Neural Network 2005, May 29, 2005, China, Lecture Notes in Computer Science, (SCI-Expand index)

[7] L. He and Z. Liu, An Effective Cache Overlapping Storage Structure for SMT Processors, Proceeding of ACIS International Conference on Computer and Information Science (ICIS 2005), pp. 300-305. (pdf)

 [8] Y. Sazeides, P. Michaud, L. He, D. Fetis, C. Ioannou, P. Charalam­bous and A. Seznec. Initial Results on the Performance Implications of Thread Migration on a Chip Multi-Core. 3rd HiPEAC Industrial Workshop, April 17, 2007. Haifa, Israel. (sildes)

[9] Yongfeng Pan, Xiaoya Fan, Liqiang He, Deli Wang, A bypass Mech­anism to Enhance Branch Predictor for SMT, In Proceeding of 12th Asia-Pacific Conference in Computer Systems Architecture, ACSAC2007, Seoul, Ko­rea, AUG, 2007, LNCS volume 4697 page 364-375, Springer, 2007. (pdf)

[10] L. He, I. Christiana, K. Marios, S. Yiannakis. Using Grid for Micro-Architecture Research, EGEE 2007, Hungary. (pdf)

[11] L. He. Boost Sequential Program Performance Using A Virtual Large Instruction Window on Chip Multicore Processor. In Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, Beijing, China, June 2008, in conjunction with 35th Inernational Symposium on Computer Architecture. (pdf)

[12] L. He. A Computation Saving Partial-Sum-Global-Update Scheme For Perceptron Branch Predictor, In proceeding of 2009 World Congress on Computer Science and Information Engineering. March 2009, Los Angeles/Anaheim, USA. ( pdf)

[13] L. He and Y. Sun. Silent Sharing: An Efficient Mechanism To Fast Sequential Program Execution on Chip Multicore Processor, In proceeding of 2009 IEEE International Conference on Information Technology and Computer Science, July, 2009, Kiev, Ukraine.

[14] L. He and C. Narisu.  Heat Spreading Aware Floorplan for Chip Multicore Processor. In proceeding of 2009 International Conference on Computer Engineering and Applications. June, 2009, Manila, Philippine. (pdf) 

[15] L. He and C. Narisu. A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors. In  8th International Conference on Advanced Parallel Processing Technologies.  August, 2009, Rapperswil, Switzerland. (pdf)

[16] L. He and G. Zhang. Parallel Branch Prediction on GPU Platform. In 2nd International Conference on High Performance Computing and Applications, Aug., 2009, Shanghai, P. R. China.(pdf)

[17] G. Zhang, L. He and Y. Zhang. Parallel Best Neighborhood Matching Algorithm Implementation on GPU Platform. In 1st International Workshop on Frontier of GPU Computing, conjunction with 10th IEEE International conference on Computer and Information Technology, June 29-July 1, 2010, UK. (pdf)

[18] L. He and Y. Zhang. A Rotate-based Best Neighborhood Matching Algorithm for High Definition Image Error Concealment. In Internation Symposium on Frontier of Computer Science, Engineering, and Applications (CSEA2010), June 29-July 1, 2010, UK. (pdf)

[19] L. He, Y. Sun and C. Zhang. Adaptive Subset Based Replacement Policy for High Performance Caching. In 1st JILP Workshop on Computer Architecture Competitions: Cache Replacement Championship, Held in conjunction with the 37th ISCA, June19-23, Saint-Malo, France, (pdf) (code) (ppt) (Rank 4 on performance for CMP with shared memory)

    

Technical Report:

[1] L. He, R. Dolbeau, and Andre Seznec, CASH Design Space Exploration, Technical Report of IRISA(No.1815) and INRIA(No.5994), September 2006.

      Patent: 

      [1] L. He, Z. Liu, and W. Hu, An Instruction Fetching Controller and Method for Simultaneous Multithreaded Processor. Chinese Patent No. ZL200410009288.5 

      Ph.D Thesis:

     My Ph.D thesis is about the front end of Simultaneously Multithreaded (SMT) Processors. The objective is to improve the overall performance or instruction throughput through optimizing the front end unit. My researches focus on three parts of the unit, instruction fetch unit, level one cache and branch predictor. I have proposed an effective fetch policy, a simple cache compression scheme, and a value base branch predictor for the front end. Through combining all these techniques, the overall performance can be improved 55%. (PDF in Chinese)

Papers that cite my work:

    [1] Yun-Huei Chen and Jong-Jiann Shieh, ICC: A Simultaneous Multithreading Fetch Engine, National Computer Symposium,NCS, 2005 Dec. 15-16, Taiwan

2009-2010学年寒假实习项目：readme.doc

Professional activities:

    Reviewer of IEEE Micro 2007

    Reviewer of  CSIE 2009 (2009 World Congress on Computer Science and Information Engineering)

    Reviewer of  International Journal of Computer & Electrical Engineering

    Reviewer of IPDPS 2009

Graduated Students:

Cha Narisu                    (master student)    Graduate at the Summer of 2009

Yanyan  Zhang (thesis), Zhongliang Yu     (master student)    Graduate at the Summer of 2010